1. Field of the Invention
The present invention relates to semiconductor integrated circuits and, in particular, to a high-Q spiral inductor structure obtained through a low-loss underlying doping profile and to methods of manufacturing the high-Q spiral inductor structure.
2. Discussion of the Related Art
FIG. 1A shows a plan view of a typical spiral inductor structure 100. FIG. 1B is a cross-section view of the FIG. 1A structure taken along line Axe2x80x94A in FIG. 1A.
The illustrated spiral inductor structure 100 includes a metal strip 102, usually aluminum or copper, that is patterned in a generally serpentine configuration. The coils of the metal strip 102 are separated from one another, and from the underlying silicon substrate 104 (see FIG. 1B), by surrounding dielectric material 106, typically silicon dioxide. The spiral inductor metal strip 102 includes a pad region 102a that provides for electrical connection to the strip 102. The strip 102 may also be connected to other conductive elements in the overall integrated circuit structure of which the inductor is a part, such as, for example, the lower conductive layer 108 shown in FIG. 1B; in the FIG. 1B structure, the inductor coil strip 102 is connected to the lower conductive layer 108 by vias 110. As further shown in FIG. 1B, the underlying substrate 104 usually comprises a layer of bulk silicon 112 with a layer of epitaxial silicon 114 formed on the bulk silicon 112.
As illustrated by the solid line 116 in FIG. 1B, the dopant profile in the silicon substrate 104 includes a first dopant concentration in the epitaxial silicon 114 that is less than a second dopant concentration of the underlying bulk silicon 112.
Conventionally, conflict arises in the realization of high quality-factor (Q) spiral inductors in a complementary-metal-oxide-semiconductor (CMOS) process flow due to the high level of dopant used in the underlying bulk silicon 112, situated underneath the epitaxial layer 114. The higher dopant concentration in the bulk silicon 112 results in a significant eddy current induced from the overlying inductor 102.
The present invention relates to improved compatibility between a standard, high density CMOS process and a high performance wireless process that realizes high-Q spiral inductors.
A high-Q spiral inductor structure in accordance with the present invention utilizes a three-layer substrate. The three-layer substrate is utilizable for CMOS circuits while at the same time minimizes eddy current induction and increases the inductor quality factor Q.
A spiral inductor structure in accordance with the present invention includes a lower layer of semiconductor material that has a first dopant concentration. An intermediate layer of semiconductor material above the lower layer has a second dopant concentration that is greater than the first dopant concentration. An upper layer of semiconductor material above the intermediate layer has a third dopant concentration that is substantially the same as the first dopant concentration. A spiral inductor is formed above the upper layer and is insulated from the upper layer by dielectric material.
The features and advantages of the present invention will be more fully appreciated upon consideration of the following detailed description of the invention and the accompanying drawings.